1. Field of Invention
The invention relates to a semiconductor light emitting device, such as a light emitting diode, including a porous semiconductor layer.
2. Description of Related Art
Semiconductor light emitting devices such as light emitting diodes (LEDs) are among the most efficient light sources currently available. Material systems currently of interest in the manufacture of high brightness LEDs capable of operation across the visible spectrum include group III-V semiconductors, particularly binary, ternary, and quaternary alloys of gallium, aluminum, indium, and nitrogen, also referred to as III-nitride materials; and binary, ternary, and quaternary alloys of gallium, aluminum, indium, arsenic, and phosphorus. Often III-nitride devices are epitaxially grown on sapphire, silicon carbide, or III-nitride substrates and III-phosphide devices are epitaxially grown on gallium arsenide by metal organic chemical vapor deposition (MOCVD) molecular beam epitaxy (MBE) or other epitaxial techniques. Often, an n-type region is deposited on the substrate, then an active region is deposited on the n-type region, then a p-type region is deposited on the active region. The order of the layers may be reversed such that the p-type region is adjacent to the substrate.
Commercial LEDs are non-ideal devices that contain many optical loss mechanisms, both within the semiconductor layers, such as active layer re-absorption and free-carrier absorption, and at semiconductor-metal interfaces where highly-reflective effective ohmic contacts are difficult to realize. Light rays trapped by total internal reflection or waveguiding are particularly impacted by these mechanisms.
FIG. 1 illustrates a light emitting device described in more detail in U.S. Pat. No. 6,229,160, which is incorporated herein by reference. The LED of FIG. 1 includes a heterostructure comprising a plurality of p- and n-type doped epitaxial layers 10 grown on a substrate, e.g. GaAs, GaP, or sapphire. The p- and n-type layers are arranged to provide a p-n junction region in or near an active region 11. A transparent substrate or layer 12, a window for light extraction (and current spreading) is the top window layer for the device. Similarly, a window layer 13 for light extraction (and current spreading) may be attached to the epitaxial layers on the side opposite the top window layer by wafer-bonding, epitaxial growth, or regrowth, to become the bottom window layer. Top and bottom electrical ohmic contacts 14, 15 attached to the window layers allow injection of electrons and holes into the p-n junction region for recombination and the subsequent generation of light from the active region.
In order to increase extraction of light from the device, the sidewalls 16 of the primary window are oriented at an angle (or angles) β relative to the vertical direction such that the area extent of the top surface 17 is greater than that of the active device area. The sidewall makes an oblique angle with respect to the heterostructure. The angle β need not be constant as a function of device height (as shown in FIG. 1), but may vary continuously according to device height to result in either partially or wholly concave or convex sidewall shapes. The sidewall orientation causes light which strikes the sidewalls to be totally internally reflected into an escape cone at the top surface of the device, as shown by ray 18 in FIG. 1. Much of the light which is totally internally reflected at the top surface is redirected into an escape cone at the sidewalls, shown by ray 19.
Though the shaping of the device shown in FIG. 1 may increase light extraction, the device has several shortcomings. First, the efficiency of the device still suffers due to the inherent absorption of contacts 14 and 15. With a commonly-used full-sheet alloyed AuZn as back contact 15, light output is reduced due to poor reflectivity. Substituting a patterned AuZn back contact (with about 20% area coverage) in conjunction with reflective Ag-based die-attach epoxy may slightly increase light output. Second, the presence of one or more thick window layers in the device can be practically realized only by high temperature growth and processing steps which can compromise the quality of the semiconductor layers by redistributing defects and dopant atoms. Third, the thickness and the lateral extent of the structure must be scaled together to maintain the proper shape. Accordingly, shaped chips are not easily scalable and are not suitable for non-square footprints. The active region area is approximately one-half of the total lateral chip extent, resulting in a doubling of the current density in the active region, which may reduce internal efficiency at high operating temperatures and currents.
Needed in the art are techniques to improve light extraction.